1. Field of the Invention
The present disclosure relates to storage system, and more specifically to a storage system utilizing single bitline based sensing techniques for reading out data.
2. Discussion of the Related Art
Storage devices include a plurality of bit lines, with each bit line having a logic state indicating the data being read from the memory. Bit lines are either single ended or differential ended. A single ended bit line is normally pre-charged to a high voltage level. In a read operation, the pre-charge on the bit line is removed and the bit line stays at a high or a low level depending upon the data stored on the bit line.
Single-ended bit line structures are adapted to various types of memories such as read only memories (ROM), a multi-port static random access memory (SRAM), and a programmable logic array (PLA). The single-ended bit line structures amplify and sense the voltage difference between a referenced bitline and a bit line coupled to the cell in which data is stored. If stored data on the bit line is ‘1’ then the bit line does not discharge. However, if the stored data on the bit line is ‘0’, the bit line discharges.
The difficulty arises when a non discharge bit line has to be read i.e. when the stored data on the bit line is ‘1’; as it has zero differential voltage if Vdd is used as the reference voltage.
FIG. 1 illustrates a conventional memory device having a single-ended sense amplifier. The single-ended sense amplifier includes a differential sense amplifier for sensing and amplifying the voltage difference between a reference voltage provided by a reference voltage generator and the sensed bit line voltage. The reference voltage generator consumes significant power hence such a memory device is inefficient. This topology is also sensitive to process variations as the reference voltage (Vref) value is dependent on the threshold voltage (Vth) of the PMOS and NMOS transistors.